IC 74157 PDF

  • No Comments

Quad 2-line to 1-line Data Selectors/multiplexers. This X24C02 device has been acquired by IC Microsystems Sdn Bhd from Xicor, Inc. The X24C02 is. The LSTTL / MSI SN54 / 74LS is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select. S, 1 •, 16, Vcc. 1I0, 2, 15, E. 1I1, 3, 14, 4I0. 1Y, 4, 13, 4I1. 2I0, 5, 12, 4Y. 2I1, 6, 11, 3I0. 2Y, 7, 10, 3I1. GND, 8, 9, 3Y. Pin, Symbol, Description. 1, S, common data.

Author: Tozilkree Akimi
Country: Laos
Language: English (Spanish)
Genre: Life
Published (Last): 23 June 2004
Pages: 18
PDF File Size: 2.84 Mb
ePub File Size: 4.83 Mb
ISBN: 377-2-66404-814-3
Downloads: 33817
Price: Free* [*Free Regsitration Required]
Uploader: Arashijas

Binary Comparators CI , Multiplexers CI

All these considerations are translated in the truth table of figure The integrated circuit is a quadruple multiplexer with 2 ways at entry of common selection.

Click here for if following lesson or in the synopsis envisaged to this ix. The stitching of this circuit is given on figure 21, while figure 22 represents its logic diagram. Figure 29 represents the diagram symbolic system and the mechanical equivalent of a multiplexer with 4 ways.

Dynamic page of welcome. Electronic forum and Poem. For example for a multiplexer with 4 waysone needs 2 entries of order. The number of the inputs of a multiplexer defines the number of ways of a multiplexer. These circuits have several inputs and only one exit.

  FX 570S PDF

Figure 25 gives the diagram symbolic system and the mechanical equivalent of a multiplexer to 2 ways. To contact the author. The first circuit uc the weak weights of A with the weak weight of B.

A multiplexer can thus switch data made up of several bits. In general, the selected entry carries in index the state corresponding to the combination of the entries of order. How to make a site? That is translated in the table of figure A multiplexer can be compared with a mechanical switch. Uc of the perso pages. Electronic forum and Infos.

The number of the entries of order is a function of the number of ways of the multiplexer.

Return to the synopsis. A binary comparator is 7157 logical circuit which carries out the comparison between 2 generally noted binary numbers A and B. Static page of welcome. When this entry is with state 1it is the data Bi which is transferred in Yi. We will see how to produce using logical doors a comparator of 2 binary digits.

In this chapter, we will examine logical circuits very much used to switch 774157 The integrated circuit is a comparator 4 bitsi. If a multiplexer has n input, it is said that it is about a multiplexer with n ways.

  DETERMINATIETABEL BLADEREN PDF

This table, one can extract the equation from the exit S following: The combinative network of figure 26 can provide the signal S.

That is to say to compare the two binary digits A and B. Thus, one can compare numbers of 8, 12, 16 bits…. The stitching and the logic diagram of this circuit are given on figure Its equation ci thus A. According to the state of the entry of selection Athe exit S recopy either the D0 entry, or the D1 entry.

Quad 2-line to 1-line data selectors / multiplexers 74157

Using one or several entries of order, one switches one of the inputs towards the icc. By putting in series two comparatorsone can compare two numbers of 8 bits. Let us examine simplest of the multiplexers, that with 2 ways. We deduce the equation from it from S following: High of page Preceding page Following page. Forms maths Geometry Physics 1.

Posted in : Sex